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SEMICONDUCTOR TECHNICAL DATA
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TMOS E-FET.TM High Energy Power FET D2PAK-SL Straight Lead
N-Channel Enhancement-Mode Silicon Gate
This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Robust High Voltage Termination * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured -- Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation
D
MTB6N60E1
Motorola Preferred Device
TMOS POWER FET 6.0 AMPERES 600 VOLTS RDS(on) = 1.2 OHM
(R)
G CASE 418C-01, Style 2 D2PAK-SL S
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage -- Continuous Gate-Source Voltage -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (1) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Thermal Resistance -- Junction to Ambient (1) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds (1) When surface mounted to an FR4 board using the minimum recommended pad size. Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 600 600 20 40 6.0 4.6 18 125 1.0 2.5 - 55 to 150 405 RJC RJA RJA TL 1.0 62.5 50 260 C/W Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ
TJ, Tstg EAS
C
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E-FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
(c)Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1997
1
MTB6N60E1
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 600 Vdc, VGS = 0 Vdc) (VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 6.0 Adc) (VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge ( (VDS = 300 Vdc, ID = 6 0 Ad , Vd , 6.0 Adc, VGS = 10 Vdc) 6.0 Adc, (VDS = 300 Vdc, ID = 6 0 Ad Vd VGS = 10 Vdc Vdc, RG = 9.1 ) ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (1) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD -- -- trr (IS = 6 0 Ad , VGS = 0 Vdc, 6.0 Adc, Vd , ( dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD -- LS -- 7.5 4.5 -- -- nH nH ta tb QRR -- -- -- -- 0.83 0.72 266 166 100 2.5 1.5 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 14 19 40 26 35.5 8.1 14.1 15.8 30 40 80 50 50 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vdc Vdc f = 1.0 MHz) Ciss Coss Crss -- -- -- 1498 158 29 2100 217 56 pF VGS(th) 2.0 -- RDS(on) VDS(on) -- -- gFS 2.0 6.0 -- 5.5 8.6 7.6 -- mhos -- 3.0 7.1 0.94 4.0 -- 1.2 Vdc mV/C Ohms Vdc V(BR)DSS 600 -- IDSS -- -- IGSS -- -- -- -- 1.0 50 100 nAdc -- 689 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time
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Motorola TMOS Power MOSFET Transistor Device Data
MTB6N60E1
TYPICAL ELECTRICAL CHARACTERISTICS
12 TJ = 25C I D , DRAIN CURRENT (AMPS) 10 8V 8 6 5V 4 2 4V 0 0 2 6 10 14 4 8 12 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 18 0 2.0 2.5 VGS = 10 V 7V 6V I D , DRAIN CURRENT (AMPS) 10 8 6 4 2 100C 25C TJ = - 55C 3.5 4.5 5.5 3.0 4.0 5.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6.0 12 VDS 10 V
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 2.5 VGS = 10 V 2.0 TJ = 100C 1.5 25C 1.0 - 55C 0.5 1.4
Figure 2. Transfer Characteristics
TJ = 25C 1.3 1.2 1.1 1.0 15 V 0.9 0.8 0 2 4 6 8 ID, DRAIN CURRENT (AMPS) 10 12 VGS = 10 V
0
0
2
4 6 8 ID, DRAIN CURRENT (AMPS)
10
12
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.5 VGS = 10 V ID = 3 A 2
10000 VGS = 0 V 1000 I DSS , LEAKAGE (nA) TJ = 125C 100C 100
1.5
1
0.5
10
25C
0 - 50
- 25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
150
1 0 100 200 300 400 500 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 600
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTB6N60E1
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
3200 Ciss C, CAPACITANCE (pF)
VDS = 0 V
VGS = 0 V
TJ = 25C
10000
TJ = 25C VGS = 0 V
Ciss
C, CAPACITANCE (pF)
2400
1000
1600
Crss
Ciss
100
Coss Crss
800 Coss 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25
10
1
10
100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
1000
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MTB6N60E1
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 Q3 0 0 6 12 18 24 VDS 30 QT, TOTAL CHARGE (nC) Q1 Q2 100 VGS 200 300 100 VDD = 300 V ID = 6 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
10
ID = 6 A TJ = 25C
td(off) tf tr td(on)
0 36
1
1
10 RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
6 5 4 3 2 1 0 0.50 VGS = 0 V TJ = 25C
I S , SOURCE CURRENT (AMPS)
0.55
0.60
0.65
0.70
0.75
0.80
0.85
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
MTB6N60E1
SAFE OPERATING AREA
VGS = 20 V SINGLE PULSE TC = 25C 10 s 10 100 s 1 ms 1.0 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 E , SINGLE PULSE DRAINN-TO-SOURCE AS AVALANCHE ENERGY (mJ) 100 I D , DRAIN CURRENT (AMPS) 450 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 ID = 6 A
dc 1000
0.1 0.1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (SECONDS) t2 DUTY CYCLE, D = t1/t2 0.1 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1 10
Figure 13. Thermal Response
3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) 150
RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
Figure 15. D2PAK Power Derating Curve
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Motorola TMOS Power MOSFET Transistor Device Data
MTB6N60E1
PACKAGE DIMENSIONS
C -B-
4
E V
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.
W
1 2 3
A
DIM A B C D E F G H J K S V W
-T-
SEATING PLANE
F
SK
G D
3 PL M
J H TB
M STYLE 2: PIN 1. 2. 3. 4.
INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.039 REF 0.100 BSC 0.080 0.110 0.018 0.025 0.280 0.360 0.276 REF 0.045 0.055 0.423 0.462
MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 1.00 REF 2.54 BSC 2.03 2.79 0.46 0.64 7.11 9.14 7.00 REF 1.14 1.40 10.75 11.75
0.13 (0.005)
GATE DRAIN SOURCE DRAIN
CASE 418C-01 ISSUE O
Motorola TMOS Power MOSFET Transistor Device Data
7
MTB6N60E1
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Motorola TMOS Power MOSFET Transistor MTB6N60E1/D Device Data

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